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This paper describes the architecture, design & implementation of two bit ternary ALU (T-ALU) slice. The proposed ALU is designed for two-bit operation & can be used for n bit operations by cascading n/2 ALU slices. This ALU is implemented the usage of C-MOS ternary logic gates (T-Gates) for ternary mathematics & good judgment circuits. Ternary gates are implemented the use of enhancement / depletion MOSFET generation, consequently proposed ALU is appropriate for LSI / VLSI implementation. Thedoi:10.5281/zenodo.6346652 fatcat:s3bs4j5zyjhl7iwmjd65ywtqhm