Power profile manipulation: a new approach for reducing test application time under power constraints

P.M. Rosinger, B.M. Al-Hashimi, N. Nicolici
2002 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper proposes a power profile manipulation approach which merges two distinct research directions in low power testing: minimization of test power dissipation and test application time reduction under power constraints. It is shown how complementary techniques can be easily combined through this approach to significantly increase test concurrency under power constraints. This is achieved in two steps: in the first step power dissipation is considered a design objective and consequently it
more » ... is minimized, result further exploited in the second step, when power becomes a design constraint under which the test application time is reduced. A distinctive feature of the proposed power profile manipulation approach is that it can be included in, and consequently improve, any existing power constrained test scheduling algorithm. Extensive experimental results using benchmark circuits, considering test-per-clock as well as test-per-scan schemes, show that by integrating the proposed power profile manipulation approach into any existing power constrained test scheduling algorithm, savings up to 41% in test application time are achieved. Low power design of complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) and systems is a well researched area [16, 18] . Testing low power ICs and systems is a relatively new research topic, which is receiving increasing attention lately [2, 3, 6-15, 17, 22, 23]. It was reported in [23] that, due to an increased activity on chip, the power dissipation during test is significantly higher than during the functional operation which constitutes an emerging yield and reliability problem [22, 23] . Another important issue in testing modern systems is the test time. With the rapidly increasing complexity of modern systems, testing becomes more time consuming which has a serious impact on the final cost of the design. Test scheduling is a commonly adopted strategy for reducing test application time by augmenting the concurrency of test activities in the system. However, increased test concurrency leads to higher power dissipation which is not tolerated by low power systems. Consequently, several solutions to the problem of power dissipation during test have been recently proposed [2, 3, 6-15, 17, 22, 23]. Within these recent solutions, two main research directions can be identified: one considering power dissipation during test an optimization objective, and the other which considers power as a design constraint under which other test parameters, such as test time, are reduced. The first category includes, although it is not limited to, test vector reordering methods [4, 6, 7, 9] which aim to increase the correlation between successive test patterns and thus reduce the power dissipation during test application. The test vector ordering is done in a post-ATPG phase, thus it does not increase the test application time. Since both power dissipation and test application time represent major issues of test, several power constrained test scheduling (PCTS) algorithms, belonging to the second research direction, were reported recently. PCTS algorithms [2, 3, 10-12, 14, 17] aim to minimize test application time under a given power constraint imposed by the package type and energy limitations. The basic idea of PCTS algorithms is to maximize the test concurrency, without exceeding the power constraint. Test scheduling is performed during system integration. Usually the embedded cores are delivered as IP blocks accompanied with test data, thus the system integrator might not have access to their internal structure. Therefore, unless the cores are pre-designed with special scan architectures, the system integrator can control the power dissipation during test only by means of test data transformations, such as test vector reordering and/or test sequence expansion. This paper introduces a new approach for reducing test application time by manipulating (changing) power profiles of test sets that are applied to every block in the system. This power profile manipulation consists of lowering, reshaping and then rotating the power profiles such that maximum power dissipation of every test is minimized at the block level and test concurrency is maximized at 1 the system level. The proposed methodology represents a general solution for the system integrator without putting any constraints on the scan architectures of the cores. While several power constrained test scheduling methods have been reported [2, 3, 10-12, 14, 17] to the best of our knowledge this is the first solution where: a) not only the average and/or peak values of power dissipation are considered, but also the shape of the power profile, and b) the test sequences' slack time is exploited via test sequence expansion for further lowering of the power profiles. The possibility of controlling the position and size of higher and lower power parts in the power profiles of system's block would allow any PCTS algorithm [2, 3, 10-12, 14, 17], to easily increase test concurrency. Moreover, a test session from a test schedule usually consists in a number of unequal length tests. The test length differences can be used to extend the shorter test sets in the test session with additional vectors. Careful selection of the additional test vectors can be used to reduce the peak power thus making room under the same power constraint for more tests. By manipulating the power profile during test scheduling, the proposed solution is a fusion between the two existing research directions in low power testing: minimizing test power dissipation [4, 6, 7, 9, 22] and minimizing test application time under power constraints [2, 3, 10-12, 14, 17]. Hence, this paper shows how complementary techniques can be easily combined to significantly increase test concurrency under given power constraints. The proposed power profile manipulation approach is not a test scheduling algorithm, rather it represents a complementary technique meant to enhance the performance of existing power constrained test scheduling algorithms. The distinctive benefit of the power profile manipulation approach is that it does not depend on the initial test sets, as well as it is independent on the test scheduling policy. Consequently, it can be equally embedded into any existing PCTS algorithm to leverage its performance. However, to be noted that this methodology is addressed only to the cases when testing is performed exclusively using ATPG-generated test vectors and where the order of the test vectors can be changed, such as testing for stuck-at faults in combinational or full-scan sequential circuits, which is still one of the most popular fault models [21] . The rest of the paper is organized as follows. Section 2 provides the background on test scheduling, test power modeling, and motivates power profile manipulation. The new approach, including a new test power approximation model, is detailed in Section 3. Section 4 shows through an example how the proposed can be integrated into existing power constrained test scheduling algorithms. To validate the proposed approach, extensive experimental data is given and interpreted in Section 5, while Section 6 concludes the paper by outlining its contributions.
doi:10.1109/tcad.2002.802256 fatcat:6d4xax7fhnbu3bpaqoue42j57y