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<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/dqy7qc7jkzal5bz3gueys3siz4" style="color: black;">Proceedings of the ACM on Programming Languages (PACMPL)</a>
Stateless Model Checking (SMC) is a verification technique for concurrent programs that checks for safety violations by exploring all possible thread interleavings. SMC is usually coupled with Partial Order Reduction (POR), which exploits the independence of instructions to avoid redundant explorations when an equivalent one has already been considered. While effective POR techniques have been developed for many different memory models, they are only able to exploit independence at the<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1145/3360599">doi:10.1145/3360599</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/m2upimc2nzajxc4jj5kdco5hta">fatcat:m2upimc2nzajxc4jj5kdco5hta</a> </span>
more »... on level, which makes them unsuitable for programs with coarse-grained synchronization mechanisms such as locks. We present a lock-aware POR algorithm, LAPOR, that exploits independence at both instruction and critical section levels. This enables LAPOR to explore exponentially fewer interleavings than the state-of-the-art techniques for programs that use locks conservatively. Our algorithm is sound, complete, and optimal, and can be used for verifying programs under several different memory models. We implement LAPOR in a tool and show that it can be exponentially faster than the state-of-the-art model checkers.
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