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This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 compressor and multiple compressors. The hierarchy multipliers is optimised in the term of speed or area of hierarchy multiplier by redesigning 4:2 compressor units and introducing a combination of 4:2 compressor and 7:3 compressor units in a Vedic multiplier block. All designs are simulated using Altera Quartus II software. The aim of this paper is to improve the performance in speed by moderatelydoi:10.1051/epjconf/201716201067 fatcat:xiwgqrvcgjcndbvmmpcbzpvqmy