In systems consisting of interacting datapaths and controllers, the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This is not possible when the controller-datapath pair is an embedded system designed as a hard core. This work facilitates the testing of controller-datapath pairs in a truly integrated fashion. The key to the approach is a careful examination of the types of gate level stuck-at faults that

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... an occur within the controller. A class of faults that are undetectable in an integrated test by traditional means is identified. These faults create faulty but functional circuits. The effect of these faults on power consumption is explored, and a method based on power analysis is given for detecting these faults. Analysis is given for three example systems. This work addresses the problem of testing systems that consist of interacting datapaths and controllers, and facilitates the testing of these controller-datapath pairs in an integrated fashion. Typically, testing of datapaths and controllers is done independently, rather than as two parts of an inseparable pair. However, the separation may not be feasible in embedded system designs where the controller-datapath is a reusable component or core to be integrated in a system-on-chip. Separate testing does not adequately cover the interface between the controller and the datapath. Few, if any, design tools address the issue of how to test datapath and controller in an integrated way. The main difficulty in integrated testing is the need to propagate controller faults through the datapath for observation at the datapath outputs. In their work on integrating controller and datapath test, Dey et. al. observed that even when the controller and datapath are 100% testable separately, the combination of them has usually much lower coverage. This degradation, in their opinion, occurs due to the correlation and dependency between the control signals [8] . In our recent work [16] we addressed the problem of integrated test, and provided a test synthesis method to allow the controller to be easily tested as part of the integrated system. However, our method required design-for-testability insertion at the controllerdatapath interface, and therefore is not appropriate for embedded cores. In our work we came across a new type of system-level redundant fault, originating in the controller, that while having no functional effect yet produces an undesirable power increase during normal system operation. This issue has been the motivation and focus of our present work. The key to our approach is a careful analysis of the system-functionally redundant faults, which are undetectable in any traditional test that treats the pair as an integrated system. What we found is that many of these faults have a significant, measurable effect on dynamic power consumption. We remark here that these faults can not be caught by IDDQ techniques [1] , which measure quiescent current. )