A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is
VLSI interconnect capacitance is becoming more significant and also increasingly subject to process variation in the deep submicron regime. A new set of capacitance models is implemented in the Magic VLSI layout tool to improve the capacitance accuracy based on 2.5D capacitance models. This involves a new technology file, equations, and search algorithms. In addition, a simple technique to extract from layout the sensitivity of interconnect parasitic capacitance to linewidth process variationdoi:10.14288/1.0067690 fatcat:sjismhemkfdv7ljw7jq43ichk4