Pipelined memory shared buffer for VLSI switches

Manolis Katevenis, Panagiota Vatsolaki, Aristides Efthymiou
1995 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication - SIGCOMM '95  
Switch chips are building blocks for computer and communication systems. Switches need internal buffering, because of output contention; shared buffering is known to perform better than multiple input queues or buffers, and the VLSI implementation of the former is not more expensive than the latter. We present a new org anization for a shared buffer with its associated switching and cut-through functions. It is simpler and smaller than wide or interleaved org anizations, and it is particularly
more » ... uitable for VLSI technologies. It is based on multiple memory banks, addressed in a pipelined fashion. The first word of a packet is transferred to/from the first bank, followed by a "wave" of similar operations for the remaining words in the remaining banks. An FPGA-based prototype is operational, while standard-cell and full-custom chips are being submitted for fabrication. Simulation of the full-custom version indicates that, even in a conservative 1-micron CMOS technology, a 64 Kbit central buffer for an 8×8 switch operates at 1 Gbps/link (worst case) and fits in 45 mm 2 including crossbar and cut-through.
doi:10.1145/217382.217406 dblp:conf/sigcomm/KatevenisVE95 fatcat:ezwb2b642zhy7d5o3m3nhdavw4