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Power management of variation aware chip multiprocessors
2008
Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08
Faced with the challenge of finding ways to use an evergrowing transistor budget, microarchitects have begun to move towards the chip multiprocessors (CMPs) as an attractive solution. CMPs have become a common way of reducing chip complexity and power consumption while maintaining high performance. Multiple cores are replicated on a single chip, resulting in a potential linear scaling of performance. Cores are becoming sufficiently small with technology scaling. As technology continues to
doi:10.1145/1366110.1366211
dblp:conf/glvlsi/PapaM08
fatcat:2ltk2pkcozca5dqxip6pwxjpuq