Design and Analysis of On-Chip CPU Pipelined Caches [chapter]

C. Ninos, H. T. Vergos, D. Nikolos
2000 IFIP Advances in Information and Communication Technology  
The access time of the first level on-chip cache usually imposes the cyc1e time of high-perfonnance VLSI processors. The only way to reduce the effect of cache access time on processor cycle time is the use of pipelined caches. A timing model for on-chip caches has recently been presented in [1]. In this paper the timing model given in [1] is extended so as pipelined caches can be handled. Also the possible pipelined architectures of a cache memory are investigated. The speedup of the pipelined
more » ... cache against the non-pipelined one is examined as a function of the pipeline depth, the organization and the physical implementation parameters.
doi:10.1007/978-0-387-35498-9_15 fatcat:6ookn5cndja4jpwtefs6kukw3m