A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter chain for various operating conditions at run time. A desired LDMC value, intended to match the critical path of the operating circuit plus a safety margin, is then chosen; a closed loop control scheme is used to maintain the desired LDMC value as chip temperature changes, by automatically adjusting the voltage

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... to the FPGA. We describe experiments using this technique on various circuits at different clock frequencies and temperatures to demonstrate its utility and robustness. Power savings between 4% and 54% for the V IN T supply are observed. * Circuits with suffix 'a' have a clock frequency of 100 MHz; circuits with suffix 'b' have a clock frequency of 66 MHz. * * Circuits are synthesized using Xilinx ISE6.2, optimized for speed All experiments are conducted at room temperature.