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Dynamic voltage scaling for commercial FPGAs
Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter chain for various operating conditions at run time. A desired LDMC value, intended to match the critical path of the operating circuit plus a safety margin, is then chosen; a closed loop control scheme is used to maintain the desired LDMC value as chip temperature changes, by automatically adjusting the voltagedoi:10.1109/fpt.2005.1568543 fatcat:zbd6vhqrwfdidmbdyrqhvvxoeu