Implementing a cache for a high-performance GaAs microprocessor

O. A. Olukotun, T. N. Mudge, R. B. Brown
1991 SIGARCH Computer Architecture News  
In the near future, microprocessor systems with very high clock rates will use multichip module (MCM) packaging technology to reduce chip-crossing delays. In this paper we present the results of a study for the design of a 250 MHz Gallium Arsenide (GaAs) microprocessor t,lrat employs h4CM technology to improve performance. The design study for the resulting two-level split cache st.arts with a baseline cache architecture and then examines the following aspects: 1) primary cache size and degree
more » ... f associativity; 2) primary data-cache write policy; 3) secondary cache size and organization; 4) primary cache fetch size; 5) concurrency between instruction and data accesses. A trace-driven simulator is used to analyze each design's performance. The results show that memory access time and page-size constraints ef-Cectively limit the size of the primary data and instruction caches to 4I<W (16KB). For such cache sizes, a write-through policy is better than a write-back policy. Three cache mechanisms that contribute to improved performance are introduced. The first is a variant of the write-through policy called write-only. This write policy provides most of the performance benefits of sub-I l o d placernenl without extra valid bits. The second, is the use of a split secondary cache. Finally, the third mechanism allows loads to pass stores without associative matching.
doi:10.1145/115953.115967 fatcat:jfblohodhfgmbinxc2zmyt5l4m