A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is
Implementing a cache for a high-performance GaAs microprocessor
SIGARCH Computer Architecture News
In the near future, microprocessor systems with very high clock rates will use multichip module (MCM) packaging technology to reduce chip-crossing delays. In this paper we present the results of a study for the design of a 250 MHz Gallium Arsenide (GaAs) microprocessor t,lrat employs h4CM technology to improve performance. The design study for the resulting two-level split cache st.arts with a baseline cache architecture and then examines the following aspects: 1) primary cache size and degreedoi:10.1145/115953.115967 fatcat:jfblohodhfgmbinxc2zmyt5l4m