Calibration method to reduce the error in logarithmic conversion with its circuit implementation

Zhou Zhao, Ashok Srivastava, Lu Peng, Saraju P. Mohanty
2018 IET Circuits, Devices & Systems  
Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator
more » ... ut any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.
doi:10.1049/iet-cds.2017.0315 fatcat:hwaa5eg3izgrli4ihf7vunyqhy