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Design verification via simulation is an important component in the development of digital systems. However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process. As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulationdoi:10.1145/217474.217520 dblp:conf/dac/Chamberlain95 fatcat:r7pbllgnnzaytedlvbd6blno4m