Parallel logic simulation of VLSI systems

Roger D. Chamberlain
1995 Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95  
Design verification via simulation is an important component in the development of digital systems. However, with continuing increases in the capabilities of VLSI systems, the simulation task has become a significant bottleneck in the design process. As a result, researchers are attempting to exploit parallel processing techniques to improve the performance of VLSI logic simulation. This tutorial describes the current state-of-the-art in parallel logic simulation, including parallel simulation
more » ... echniques, factors that impact simulation performance, performance results to date, and the directions currently being pursued by the research community.
doi:10.1145/217474.217520 dblp:conf/dac/Chamberlain95 fatcat:r7pbllgnnzaytedlvbd6blno4m