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Modeling and Formal Control of Partial Dynamic Reconfiguration
<span title="">2010</span>
<i title="IEEE">
<a target="_blank" rel="noopener" href="https://fatcat.wiki/container/ek7djgoan5ehpihkol2k4a7rm4" style="color: black;">2010 International Conference on Reconfigurable Computing and FPGAs</a>
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This paper introduces an approach for the safe design and modeling of dynamically reconfigurable FPGA based Systems-on-Chip. This approach is carried out in a design framework, GASPARD2, dedicated to high-performance embedded systems modeling using the OMG standard profile UML/MARTE. Information employed by the reconfiguration mechanism is identified to be extracted from MARTE models in order to synthesize a controller using a formal technique which significantly simplifies the correct design
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... reconfiguration control. This methodology is then demonstrated in a case study.
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