Low-power circuits and technology for wireless digital systems As CMOS technology scales to deep-submicron dimensions, designers face new challenges in determining the proper balance between aggressive high-performance transistors and lower-performance transistors to optimize system power and performance for a given application. Determining this balance is crucial for battery-powered handheld devices in which transistor leakage and active power limit the available system performance. This paper

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... explores these questions and describes circuit techniques for low-power communication systems which exploit the capabilities of advanced CMOS technology.