A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

Artur Podobas, Kentaro Sano, Satoshi Matsuoka
<span title="">2020</span> <i title="Institute of Electrical and Electronics Engineers (IEEE)"> <a target="_blank" rel="noopener" href="https://fatcat.wiki/container/q7qi7j4ckfac7ehf3mjbso4hne" style="color: black;">IEEE Access</a> </i> &nbsp;
With the end of both Dennard's scaling and Moore's law, computer users and researchers are aggressively exploring alternative forms of computing in order to continue the performance scaling that we have come to enjoy. Among the more salient and practical of the post-Moore alternatives are reconfigurable systems, with Coarse-Grained Reconfigurable Architectures (CGRAs) seemingly capable of striking a balance between performance and programmability. In this paper, we survey the landscape of
more &raquo; ... We summarize nearly three decades of literature on the subject, with a particular focus on the premise behind the different CGRAs and how they have evolved. Next, we compile metrics of available CGRAs and analyze their performance properties in order to understand and discover knowledge gaps and opportunities for future CGRA research specialized towards High-Performance Computing (HPC). We find that there are ample opportunities for future research on CGRAs, in particular with respect to size, functionality, support for parallel programming models, and to evaluate more complex applications. INDEX TERMS Coarse-grained reconfigurable architectures, CGRA, FPGA, computing trends, reconfigurable systems, high-performance computing, post-Moore. Recently, a particular branch of reconfigurable architecture -the Field-Programmable Gate Arrays (FPGAs) [9] -has experienced a surge of renewed interest for use in High-Performance Computing (HPC), and recent research has shown performance-or power-benefits for multiple applications [10]-[14]. At the same time, many of the limitations that FPGAs have, such as slow configuration times, long compilations times, and (comparably) low clock frequencies, remain unsolved. These limitations have been recognized for decades (e.g., [15]-[17]), and have driven forth a different branch of reconfigurable architecture: the Coarse-Grained Reconfigurable Architecture (CGRAs). CGRAs trade some of the flexibility that FPGAs have to solve their limitations. A CGRA can operate at higher VOLUME 8, 2020 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 146720 VOLUME 8, 2020
<span class="external-identifiers"> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2020.3012084">doi:10.1109/access.2020.3012084</a> <a target="_blank" rel="external noopener" href="https://fatcat.wiki/release/xx6k4lxbjbc4tjebbymp42w634">fatcat:xx6k4lxbjbc4tjebbymp42w634</a> </span>
<a target="_blank" rel="noopener" href="https://web.archive.org/web/20210718015729/https://ieeexplore.ieee.org/ielx7/6287639/8948470/09149601.pdf" title="fulltext PDF download" data-goatcounter-click="serp-fulltext" data-goatcounter-title="serp-fulltext"> <button class="ui simple right pointing dropdown compact black labeled icon button serp-button"> <i class="icon ia-icon"></i> Web Archive [PDF] <div class="menu fulltext-thumbnail"> <img src="https://blobs.fatcat.wiki/thumbnail/pdf/e0/5b/e05bb191516dc65c71cb2d6f8010a5b23cd41389.180px.jpg" alt="fulltext thumbnail" loading="lazy"> </div> </button> </a> <a target="_blank" rel="external noopener noreferrer" href="https://doi.org/10.1109/access.2020.3012084"> <button class="ui left aligned compact blue labeled icon button serp-button"> <i class="unlock alternate icon" style="background-color: #fb971f;"></i> ieee.com </button> </a>