Design and Simulation of Power efficient All Digital Phase Locked Loops (ADPLL)

M Ullas, Krishnakumar, Ramesha C³
International Research Journal of Engineering and Technology (IRJET)   unpublished
We presents a new^generalised power efficient ADPLL design & Simulation^using Verilog*. Xilinx ISE 10.1 Simulator is^used for simulating Verilog Code and is synthesized using Cadence RTL compiler using gpdk 45 nm technology. To validate its functionality, verification and simulation is done by using^the Cadence IES (Incisive Enterprise Simulator) tool. This paper gives the details of basic building^blocks of the absolute ADPLL*design. And the planned power optimized clock gating technique*that
more » ... ing technique*that is implemented in the Digital loop filter without^altering the performance of overall system. The power^consumption of this ADPLL is 0.704 μW at a center frequency*(fc) of 625 KHz. The total chip area is 207 μm².