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The effect of LUT and cluster size on deep-submicron FPGA performance and density
2000
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays - FPGA '00
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cluster-based island-style FPGAs [4] we look at the effect of lookup table (LUT) size and cluster size (number of LUTs per cluster) on the speed and logic density of an FPGA. Although this question was addressed some time ago in [17] [18] [12] [13] [10] and [22], several reasons compelled us to revisit the issue. First,
doi:10.1145/329166.329171
dblp:conf/fpga/AhmedR00
fatcat:vvvzkqslgfb7do5prbs25jrs3q