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Performance Analysis of Alternate Repeaters for On-Chip Interconnections in Nanometer Technologies
2015
Procedia Materials Science
As the geometries of integrated circuits continue to shrink into the deep nanometer regime, the impact of on-chip interconnects is dominant on the overall system performance. This paper explores the power-delay trade-off in alternate repeater insertion techniques. The repeaters are placed along global on-chip interconnects to compensate the loss in the wires and to regenerate the signal strength. All the repeater insertion techniques with 3-pi RC distributed interconnect model are implemented
doi:10.1016/j.mspro.2015.06.065
fatcat:3zfmxgefibfprehryl3aciustm