A DPLL with a Modified Phase Frequency Detector to Reduce Lock Time
록 시간을 줄이기 위한 변형 위상 주파수 검출기를 가진 DPLL

Md. Tariq Hasan, GoangSeog Choi
2013 Journal of the Institute of Electronics and Information Engineers  
A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The
more » ... or simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took 0.304 µs to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of 2.144 µs to lock with a maximum jitter of approximately 0.1245 ns.
doi:10.5573/ieek.2013.50.10.076 fatcat:vg4wi4nh6rejralyiaxcodvgoa