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Low-latency wireless 3D NoCs via randomized shortcut chips
2014
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014
In this paper, we demonstrate that we can reduce the communication latency significantly by inserting a fraction of randomness into a wireless 3D NoC (where CMOS wireless links are used for vertical inter-chip communication) when considering the physical constraints of the 3D design space. Towards this end, we consider two cases, namely 1) replacing existing horizontal 2D links in a wireless 3D NoC with randomized shortcut NoC links and 2) enabling full connectivity by adding a randomized NoC
doi:10.7873/date.2014.286
dblp:conf/date/MatsutaniKFKTKBMA14
fatcat:uctcyjrkxffjnmgcznjvkugkia