SRAM delay fault modeling and test algorithm development

Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, Cheng-Wen Wu
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)  
With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of ¡ £ ¢ ¥ ¤¦ Read/Write operations, where ¡ is the number of words and ¦ is the
more » ... ds and ¦ is the word count in a row. §¨ © Read/Write operations, where¨is the number of words and
doi:10.1109/aspdac.2004.1337548 fatcat:kjqqnv2e4ja5tjbx3pmyvsr6pi