Variation-aware speed binning of multi-core processors

John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta
2010 2010 11th International Symposium on Quality Electronic Design (ISQED)  
Number of cores per multi-core processor die, as well as variation between the maximum operating frequency of individual cores, is rapidly increasing. This makes performance binning of multi-core processors a non-trivial task. In this paper, we study, for the first time, multi-core binning metrics and strategies to evaluate them efficiently. We discuss two multi-core binning metrics with high correlation to processor throughput for different types of workloads and different process variation
more » ... rocess variation scenarios. More importantly, we demonstrate the importance of leveraging variation model data in the binning process to significantly reduce the binning overhead with a negligible loss in binning quality. For example, we demonstrate that the performance binning overhead of a 64-core processor can be decreased by 51% and 36% using the proposed variationaware core clustering and curve fitting strategies respectively. Experiments were performed using a manufacturing variation model based on real 65nm silicon data.
doi:10.1109/isqed.2010.5450442 dblp:conf/isqed/SartoriPKG10 fatcat:kipzdnjutjho3jvklhdeqrimqm