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Ultra-Low Voltage VDCC Design by Using DTMOS
2016
Acta Physica Polonica. A
Preserved Fulltext
In this paper, a new ultralow voltage and ultralow power voltage differencing current conveyor based on dynamic threshold voltage MOS transistors was proposed. The simulations were performed by using LTSpice Program with TSMC CMOS 0.18 µm process parameters. A new notch filter configuration was also presented as an application for the proposed voltage differencing current conveyor. The power consumption of proposed voltage differencing current conveyor was simply 12.42 nW at symmetric ±0.2 V
doi:10.12693/aphyspola.130.223
fatcat:bxol5c5wrfautlt62sbwo6n6w4