A 390-mm/sup 2/, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture

T. Kirihata, G. Mueller, B. Ji, G. Frankowsky, J.M. Ross, H. Terletzki, D.G. Netis, O. Weinfurtner, D.R. Hanson, G. Daniel, L.L.-C. Hsu, D.W. Sotraska (+7 others)
1999 IEEE Journal of Solid-State Circuits  
A 390-mm 2 , 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic random access memory (DRAM) (SDRAM) has been fabricated in fully planarized 0.175-m, 8F 2 trench cell technology. The 1-Gb SDRAM employs a hybrid bitline architecture with 512 cells/local-bitline (LBL). Four LBL pairs are connected through multiplexers to each sense amplifier (SA). Two of the LBL pairs are coupled to the SA by wiring over two other LBL pairs using hierarchical bitlines. This results in a reduction of the
more » ... er of the SA's to 1/4, reducing the chip size by 6%. A hierarchical column-select-line scheme is incorporated with a hierarchical dataline (MDQ) architecture. This makes 16-bank organization possible while sharing hierarchical column decoders and second sense amplifiers. A hierarchical 8-b prefetch scheme employs four MDQ's for each read-write drive (RWD) and two RWD's for each DQ. This reduces the frequencies of the MDQ's and the RWD's to 1/8 and 1/2, respectively. A 1-V swing signaling on the RWD is used to reduce the burst current by 18 mA. The 1-V swing signaling is successfully converted to 2.1 V with self-timed first-in, first-out circuitry. The hardware data demonstrate 400-Mb/s/pin operation with a 16-mm TSOP-II package. Seamless burst operation at various frequencies has also been confirmed. These features result in a 1.6-Gb/s data rate for 2 2 232 200-MHz DDR operation with a cell/chip area efficiency of 67.5%. Index Terms-Double-data-rate (DDR), dynamic random access memory (DRAM), hierarchical column-select-line (CSL), hybrid bitline, low voltage, 1 Gb, prefetch, synchronous DRAM. Toshiaki Kirihata (A'92-SM'99) received the B.S. and M.S. degrees in precision engineering from Shinshu University, Nagano, Japan, in 1984 and 1986, respectively. In 1986, he joined IBM Research, Tokyo Research Laboratory, IBM Japan, Ltd. There, he was involved in research and development related to CMOS VLSI technology and circuit design. From 1987 to 1989, he worked on the circuit design and characterization of a 22-ns, 1-Mb CMOS high-speed DRAM with researchers and engineers at the IBM
doi:10.1109/4.799866 fatcat:zwrjvjrsibervcs5erg74bfn5m