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Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache
2014
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture
Recent research advocates large die-stacked DRAM caches in manycore servers to break the memory latency and bandwidth wall. To realize their full potential, diestacked DRAM caches necessitate low lookup latencies, high hit rates and the efficient use of off-chip bandwidth. Today's stacked DRAM cache designs fall into two categories based on the granularity at which they manage data: block-based and page-based. The state-of-the-art block-based design, called Alloy Cache, colocates a tag with
doi:10.1109/micro.2014.51
dblp:conf/micro/JevdjicLKF14
fatcat:od75rrrhhjebrezmmblgv4tvna