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Conference on Optoelectronic and Microelectronic Materials and Devices, 2004.
Scanning capacitance microscopy (SCM) measurement is a proposed tool for dopant profile extraction for semiconductor material. The influence of interface traps on SCM dC/dV data is still unclear. In this paper we report on the simulation work used to study the nature of SCM dC/dV data in the presence of interface traps. A technique to correctly simulate dC/dV of SCM measurement is then presented based on our justification. We also analyze how charge of interface traps surrounding SCM probedoi:10.1109/commad.2004.1577514 fatcat:e3y6cvdgonadfnzpn7bq56hgoi