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A fully-integrated digital-intensive polar Doherty transmitter

Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Michael Polushkin, Lei Zhou, Mustafa Acar, Rene van Leuken, Morteza S. Alavi, Leo de Vreede
2017 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  

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This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40 nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is
more » ... 1.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20-MHz 64-QAM signal, the measured EVM is better than −30 dB while the average drain efficiency is 24%.
doi:10.1109/rfic.2017.7969051 fatcat:4yuy4hasufdpvomdet3srxr4c4
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Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Michael Polushkin, Lei Zhou, Mustafa Acar, Rene van Leuken, Morteza S. Alavi, Leo de Vreede. "A fully-integrated digital-intensive polar Doherty transmitter." 2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) (2017)