An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects

N. Houarche, M. Comte, M. Renovell, A. Czutro, P. Engelke, I. Polian, B. Becker
2009 2009 27th IEEE VLSI Test Symposium  
In this paper a new electrical model is proposed to be used in fault size based fault simulation of crosstalk aggravated resistive short defects. The electrical behavior of the defect is first described and analyzed in details. Then an electrical model is proposed allowing to efficiently compute the critical resistance determining the range of detectable short resistance. The model is validated by comparison with SPICE simulations. 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00
doi:10.1109/vts.2009.57 dblp:conf/vts/HouarcheCRCEPB09 fatcat:4jlyj72oejcxbpb6kcwe3opsea