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This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. Testing of embedded cores is achieved using the transparency properties of surrounding cores. At the core level, testability and transparency can be achieved by reusing existing logic inside the core, and providing different versions of the core having different area overheads and transparency latencies. At the chip level, thedoi:10.1145/277044.277190 dblp:conf/dac/GhoshDJ98 fatcat:squmhwp62fdenl7s5m55b6uvee