A fast and low cost testing technique for core-based system-on-chip

Indradeep Ghosh, Sujit Dey, Niraj K. Jha
1998 Proceedings of the 35th annual conference on Design automation conference - DAC '98  
This paper proposes a new methodology for testing a core-based system-on-chip (SOC), targeting the simultaneous reduction of test area overhead and test application time. Testing of embedded cores is achieved using the transparency properties of surrounding cores. At the core level, testability and transparency can be achieved by reusing existing logic inside the core, and providing different versions of the core having different area overheads and transparency latencies. At the chip level, the
more » ... technique analyzes the topology of the SOC to select the core versions that best meet the user's desired test area overhead and test application time objectives. Application of the method to example SOCs demonstrates the ability to design highly testable SOCs with minimized test area overhead, minimized test application time, or a desired trade-off between the two. Significant reduction in area overhead and test application time compared to an existing SOC testing technique is also demonstrated.
doi:10.1145/277044.277190 dblp:conf/dac/GhoshDJ98 fatcat:squmhwp62fdenl7s5m55b6uvee