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Energy recovering ASIC design
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings.
Dissipation in the clock tree and state elements of ASIC designs is often a significant fraction of total energy consumption. We propose a methodology for recovering most of this energy by using a novel energy recovering flip-flop and a novel single-phase resonant clock generator. As our state element has near-zero energy consumption when the input data is not switching, it provides the savings of clock gating approaches without the additional complexity of implementing clock gating in the
doi:10.1109/isvlsi.2003.1183364
dblp:conf/isvlsi/ZieslerKP03
fatcat:5cu463kwurdobj7fd74qwwnhm4