Area-Efficient Hardware Architectures of MISTY1 Block Cipher

A. Yasir, N. Wu, X. Chen, M. Rehan Yahya
2018 Radioengineering  
In this paper, state-of-the-art hardware implementations of MISTY1 block cipher are presented for areaconstrained wireless applications. The proposed MISTY1 architectures are characterized of highly optimized transformation functions i.e. FL and {FO-XOR-EKG}. The FL function re-utilizes logic AND-OR-XOR combinations whereas {FO-XOR-EKG} function explores 2 × compact design schemes for s-boxes implementation. A Combined Substitution Unit (CSU) and threshold area implementation are proposed for
more » ... boxes based on Boolean reductions and Common Sub-expression Eliminations (CSEs). Besides, {FO-XOR-EKG} function is designed for manifold operations of FO / FI functions, 32-bit XOR operation and extended key generation thereby reducing the area. Hardware implementations on ASIC 180nm, 1.8V standard library cell realized compact and threshold MISTY1 designs constituting 1853 and 1546 NAND gates with throughput values of 41.6 Mbps and 4.72 Mbps respectively. A comprehensive comparison with existing cryptographic hardware designs establishes that the proposed MISTY1 architectures are the most area-efficient implementations till date. . His research interests include circuit design and optimization, FPGA and ASIC implementations, cryptography and network security. Ning WU received B.S. and M.S. degrees in 1982 and 1985 from the University of Science and Technology, China. She is currently a Professor in the College of Electronic and Information Engineering, NUAA. Her research interests include digital system design, electronic system integration and ASIC implementation. Xin CHEN received his B.S. degree and Ph.D. degree in 2005 and 2010 from the Southeast University, China. He is currently an associate professor in the College of Electronic and Information Engineering, NUAA. His research interests mainly include digitally controlled phase-locked loop, low power circuit design. Muhammad Rehan YAHYA did his BS and MS from COMSATS Institute of Information Technology, Islamabad and UET Taxila, Pakistan. Currently, he is a doctoral student in the College of Electronic and Information Engineering, NUAA. His research interests include FPGA and ASIC implementations, reconfigurable hardware design and Network-on Chip (NOC).
doi:10.13164/re.2018.0541 fatcat:epho4u7jzbc23h3j54x6vmviyi