A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf
.
Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs
2014
Research Journal of Applied Sciences Engineering and Technology
This study describes the design of high speed FIR filter using parallel prefix adders and factorized multiplier. The fundamental component in constructing any high speed FIR filter consists of adders, multipliers and delay elements. To meet the constraint of high speed performance and low power consumption parallel prefix adders are more suitable. This study focus the design of new Parallel Prefix Adder (PPA) and new multiplier cell called factorized multiplier with minimal depth algorithm and
doi:10.19026/rjaset.7.589
fatcat:fjazzho3hvfxzgiykobfbea5iy