The hierarchical h-adaptive 3-D boundary element computation of VLSI interconnect capacitance

Jinsong Hou, Zeyi Wang, Xianlong Hong
1999 Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)  
In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The Boundary Element Method(BEM) is an effective tool for solving Laplacian' s equation applied in the parasitic capacitance extraction. In this paper, a hierarchical h-adaptive BEM is presented . It constructs a 3-D linear hierarchical shape function based on constant boundary element and uses previous computations and
more » ... mputations and solutions. Hence, it reduces much computation in adaptive procedure. Besides, a combination of residualtype estimator and reduced Z-Z error estimator for more reliable and efficient estimation of error is presented. Some numerical results show that this method is effective.
doi:10.1109/aspdac.1999.759719 dblp:conf/aspdac/HouWH99 fatcat:6ktug7ak7jb5jd56olgyyd2ilq