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Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00
Caching and other latency tolerating techniques have been quite successful in maintaining high memory system performance for general purpose processors. However, TLB misses have become a serious bottleneck as working sets are growing beyond the capacity of TLBs. This work presents one of the first attempts to hide TLB miss latency by using preloading techniques. We present results for traditional next-page TLB miss preloading -an approach shown to cut some of the misses. However, a keydoi:10.1145/339647.339666 fatcat:infqwgzj2bbargccxvrakumxxm