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In today's deep sub-micron designs, large amounts of switching activity may cause a substantial voltage drop on the power rails, also called power droop. Faults that may result from a power droop include delay faults caused by the increased propagation delays from the reduced supply voltage. In order to assess the performance of a manufactured chip, its worst-case droop condition should be tested by applying a specific input pattern which can cause maximum switching activity. On the contrary,doi:10.1109/test.2007.4437597 dblp:conf/itc/LiFH07 fatcat:plgx2zpfdrfy3p47wruexvw7si