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In this paper we propose an architecture for the computation of the double-precision floating-point multiply-add fused (MAF) operation A + (B × C) that permits to compute the floating-point addition with lower latency than floating-point multiplication and MAF. While previous MAF architectures compute the three operations with the same latency, the proposed architecture permits to skip the first pipeline stages, those related with the multiplication B × C, in case of an addition. For instance,doi:10.1109/arith.2005.22 dblp:conf/arith/BrugueraL05 fatcat:f3wzrznfqrh57jycri6ap3zezi