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A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering
2011
IEEE Transactions on Image Processing
This paper presents an efficient and scalable design for histogram-based bilateral filtering (BF) and joint BF (JBF) by memory reduction methods and architecture design techniques to solve the problems of high memory cost, high computational complexity, high bandwidth, and large range table. The presented memory reduction methods exploit the progressive computing characteristics to reduce the memory cost to 0.003%-0.020%, as compared with the original approach. Furthermore, the architecture
doi:10.1109/tip.2011.2159226
pmid:21659030
fatcat:qwa6mobc7bff7lxfgy3oodsh6i