Data flow on a queue machine
Bruno R. Preiss, V. C. Hamacher
SIGARCH Computer Architecture News
An execution model that supports program reentrancy, recursion, and automatic run-time loop unravelling is described. This execution model is based on queue machines that execute acyclic data-flowg raphs. The use of separate instruction and data token spaces allows program reentrancy. Execution environments called contexts execute acyclic data-flowg raphs associated with high-levelc ode blocks. Iteration and function activation are implemented by the dynamic creation of contexts and do not
... re the use of tagged tokens. Am ultiprocessor architecture that supports this execution model is proposed. The system architecture is based on a partitioned ring in which each partition of the ring is a conventional processor/memory bus. The proposed architecture has been simulated in software. A number of test programs have been developed and their execution on the proposed architecture has been evaluated. The performance of the proposed architecture with various numbers of processing elements is described. In addition, a number of task scheduling algorithms are presented and evaluated. The proposed architecture has been simulated in software. A number of test programs were derivedt od emonstrate the performance of the architecture when executing programs containing certain specialized forms of parallelism. These simple programs were used to evaluate the performance of a number of context scheduling algorithms. Finally,t he execution of twom ore complexp rograms containing the kinds of parallelism modelled by the simple programs was simulated. Queue Machines Aq ueue machine uses implicit referencing to an operand queue in a manner analogous to the way a stack machine uses an operand stack. Operands for the current instruction are to be found at the front of an operand queue. Results of instructions are placed at the rear of the operand queue. This simple queue machine execution model is extended by associating with the result of each instruction a priority.T he destination of the result is a position in the operand queue determined from the priority of the result. Thus, a result can be inserted anywhere in the queue. Operands are only deleted from the front of the queue. Ap roblem with the prioritized queue is that insertions in the middle of the queue require the relocation of a potentially large number of operands. However, this can be avoided. Let the operand queue occupyc ontiguous memory locations. The address of the front of the queue is held in a front of queue (FOQ)r egister.A no perand fetch involves reading the contents of the memory location specified by the FOQ register and then incrementing the FOQ register. Instructions shall consist of twop arts, an operation code part, and a result priority part. The result priority part consists of a number of destination offset fields (the result of an instruction can be inserted into the operand queue in more than one position). Each destination address for the result is computed by adding the destination offset field of the instruction to the contents of the FOQ register.T hus, the task of insertion into the operand queue has been simplified from that of searching a prioritized queue to that of performing a simple offset calculation. However, there is no guarantee that the result stored by one instruction does not overwrite that of an earlier instruction. Furthermore, there is no guarantee that there are no empty spaces in the queue. That is, there is no guarantee that the content of the memory location indicated by the FOQ pointer is avalid operand. Atechnique for resolving these difficulties will be givenlater. As an example of the prioritized queue execution model consider the following instruction sequence, which computes the expression (x + y) ⋅ (x − z).