Smart-Cache: Optimising Memory Accesses for Arbitrary Boundaries and Stencils on FPGAs

Syed Waqar Nabi, Wim Vanderbauwhede
2019 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)  
A key requirement for high performance on FPGAs is to maintain continuous data streaming from the DRAM. An impediment in many computations, especially in the scientific computing domain, is irregular stencils and boundary conditions, requiring memory accesses that are random, redundant, or both. To address this problem, we present Smache, a novel smartcaching framework that uses FPGA on-chip memory resources for optimising access for arbitrary stencil shapes and boundary conditions. We propose
more » ... combination of stream and static buffers, and it is the latter that allows arbitrarily large offsets in stencils. The architecture is complemented by a formal model for determining buffer configuration. We propose a hybrid use of the block and distributed RAM on the FPGA. The design is validated for a 2D grid, 4-point stencil with circular boundaries.
doi:10.1109/ipdpsw.2019.00024 dblp:conf/ipps/NabiV19 fatcat:24gwvhgmujgn5j5yca2h5f6h6q