This paper describes the data acquisition system planned for the SLD detector, which is being constructed for use with the SLAC Linear Collider (SLC). Analog electronics, heavily incorporating hybrid and custom VLSI circuitry, is mounted on the detector itself. Extensive use is made of multiplexing through optical fibers to a FASTBUS readout system. The low repetition rate of the SLC allows a relatively simple software-based trigger. Hardware and software processors within the acquisition

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... s are used to reduce the large volume of data per event and to calibrate the electronics. A farm of microprocessors is used for full reconstruction of a sample of events prior to transmission to the host.