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Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process
2014
PLoS ONE
The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 mm CMOS technology achieves 3.44 mV
doi:10.1371/journal.pone.0108634
pmid:25299266
pmcid:PMC4191981
fatcat:z2p7jbocbfgv5axrlm4pesv7ai