Post-silicon Validation Procedure for a PWL ASIC Microprocessor Architecture

Omar David Lifschitz, Juan Agustin Rodriguez
2011 IEEE Latin America Transactions  
In this paper, we present the environment set for validation and testing a particular ASIC that implements a piecewise linear (PWL) architecture. Description for a package debug propose is included. Methodologies for power consumption and maximum operation frequency estimation, based on laboratory measurements, are described.
doi:10.1109/tla.2011.5993733 fatcat:cfagmt7ynbfe5iwjuiprvgfvsy