A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation

David Bull, Shidhartha Das, Karthik Shivshankar, Ganesh Dasika, Krisztian Flautner, David Blaauw
2010 2010 IEEE International Solid-State Circuits Conference - (ISSCC)  
Razor [1-3] is a hybrid technique for dynamic detection and correction of timing errors. A combination of error-detecting circuits and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused guardbands. Canary or tracking circuits [4] [5] can compensate for certain manifestations of PVT variation. However they still require substantial margining to account for
more » ... ving or localized events, such as Ldi/dt, local IR drop, capacitive coupling, or PLL jitter. These events are often transient, and while the pathological case of all occurring simultaneously is extremely unlikely, it cannot be ruled out. A Razor system can survive both fast-moving and transient events, and adapt itself to the prevailing conditions, allowing excess margins to be reclaimed. The savings from margin reclamation can be realized either as a per device power efficiency (higher throughput same VDD, same throughput lower power), or as parametric yield improvement for a batch of devices.
doi:10.1109/isscc.2010.5433919 dblp:conf/isscc/BullDSDFB10 fatcat:boxheevpjbashdyb4npbz7tgmm