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A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
2010
2010 IEEE International Solid-State Circuits Conference - (ISSCC)
Razor [1-3] is a hybrid technique for dynamic detection and correction of timing errors. A combination of error-detecting circuits and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused guardbands. Canary or tracking circuits [4] [5] can compensate for certain manifestations of PVT variation. However they still require substantial margining to account for
doi:10.1109/isscc.2010.5433919
dblp:conf/isscc/BullDSDFB10
fatcat:boxheevpjbashdyb4npbz7tgmm