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A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
1996
Proceedings of the 33rd annual conference on Design automation conference - DAC '96
This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful functional decomposition algorithm. The impact of decomposition is enhanced by a preceding collapsing step. To decompose functions for small depth and area, we present an iterative, BDD-based variable partitioning procedure. The procedure optimizes the variable partition for each bound set size by iteratively exchanging variables
doi:10.1145/240518.240657
dblp:conf/dac/LeglWE96
fatcat:x6nnmh4r4faubn6if5svyislue