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In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combiningdoi:10.1109/sies.2008.4577696 dblp:conf/sies/NemerCSB08 fatcat:abefj3jerngxxblm7irqy4t3la