Inter-task WCET computation for a-way instruction caches

Fadia Nemer, Hugues Casse, Pascal Sainrat, Jean Paul Bahsoun
2008 2008 International Symposium on Industrial Embedded Systems  
In hard real-time applications, Worst Case Execution Time (WCET) is used to check time constraints of the whole system but is only computed at the task level. As most WCET computation methods assume a conservative approach to handle the processor state before the execution of a task, the inter-task analysis of long effect hardware features should improve the accuracy of the result. As an example, we propose to analyze the behavior of an A-way associative instruction cache, by combining
more » ... combining inter-and intra-task instruction cache analysis. The aim is to estimate more accurately the number of cache misses due to task chaining by considering task Entry and Exit states along the inter-task analysis. The initial tasks WCETs can be computed by any existing single-task approach that models the instruction cache behavior. A second method is also introduced in this paper which consists in injecting the inter-task cache states in the intratask WCET analysis, to get more precise numbers.
doi:10.1109/sies.2008.4577696 dblp:conf/sies/NemerCSB08 fatcat:abefj3jerngxxblm7irqy4t3la