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Running at-speed functional tests has shown to be a very effective method to detect faulty chips. In our previous paper we presented a methodology for generating functional tests aimed at hard to detect gate level faults in the control logic of a processor. In that methodology gate level tests were mapped to the register transfer level ( RTL ) and a faulty RTL model was built. The propagation constraints of the fault through the design were captured as linear temporal logic ( LTL ) properties.doi:10.1109/test.2013.6651915 dblp:conf/itc/PrabhuA13 fatcat:4sf7huv3bveyfpmoflknjjq4ua