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A high-performance low-power nanophotonic on-chip network
2009
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09
On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughputoptimized circuit-switched subnetwork supports throughputsensitive data transfer. Iris'
doi:10.1145/1594233.1594305
dblp:conf/islped/LiWSMVFPS09
fatcat:csin272uo5gcraf6mqkcivsf3m