A high-performance low-power nanophotonic on-chip network

Zheng Li, Jie Wu, Li Shang, Alan R. Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
2009 Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design - ISLPED '09  
On-chip communication, including short, often-multicast, latency-critical coherence and synchronization messages, and long, unicast, throughput-sensitive data transfer, limits the power efficiency and performance scalability of many-core chip-multiprocessor systems. This article presents Iris, a CMOS-compatible high-performance low-power nanophotonic on-chip network. Iris' linear-waveguide-based throughputoptimized circuit-switched subnetwork supports throughputsensitive data transfer. Iris'
more » ... nar-waveguide-based WDM broadcast-multicast subnetwork optimizes latency-critical traffic and supports the circuit setup of circuit-switched communication. Overall, the proposed design delivers an on-chip communication backplane with high power efficiency, low latency, and excellent throughput.
doi:10.1145/1594233.1594305 dblp:conf/islped/LiWSMVFPS09 fatcat:csin272uo5gcraf6mqkcivsf3m