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Efficient digit-serial normal basis multipliers over binary extension fields
2004
ACM Transactions on Embedded Computing Systems
In this article, two digit-serial architectures for normal basis multipliers over GF(2 m ) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and
doi:10.1145/1015047.1015053
fatcat:7tkcroydxbh5dbousx6gjwjwbe