Efficient digit-serial normal basis multipliers over binary extension fields

Arash Reyhani-Masoleh, M. Anwar Hasan
2004 ACM Transactions on Embedded Computing Systems  
In this article, two digit-serial architectures for normal basis multipliers over GF(2 m ) are presented. These two structures have the same gate count and gate delay. We also consider two special cases of optimal normal bases for the two digit-serial architectures. A straightforward implementation leaves gate redundancy in both of them. An algorithm that can considerably reduce the redundancy is also developed. The proposed architectures are compared with the existing ones in terms of gate and
more » ... time complexities. A preliminary version of this article has appeared in Reyhani-Masoleh and Hasan [2002b] .
doi:10.1145/1015047.1015053 fatcat:7tkcroydxbh5dbousx6gjwjwbe