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A Hardware Structure for FAST Protocol Decoding Adapting to 40Gbps Bandwidth
2017
DEStech Transactions on Computer Science and Engineering
FAST protocol is a kind of Data Compression Protocols which is widely used in Highfrequency trading. So far, implements of fast protocol decoding mainly depend on software. On the other hand, transmission delay of decoding can be effectively decreased by customized hardware instead of software. However, most of FPGA hardware architectures are serial. A parallel FPGA hardware structure for fast protocol decoding adapting to 40Gbps bandwidth is proposed in this paper. The structure includes 3
doi:10.12783/dtcse/csma2017/17357
fatcat:lt2vcrtxcvedzlsdwnjcm2flte